The market for mobile satellite communication systems appears promising. There are, however, serious technical problems to be solved, for example demodulation capability under low C/N conditions indispensable for overcoming fading or transmission attenuation caused by multipath or blocking.
Referring now to FIG. 12, which shows a conventional demodulation circuit, 1 is an oscillator which oscillates at approximately the frequency of the carrier, 2 is a quasi-coherent detection circuit, 3 is an A/D converter, 4 is a M-th power complex multiplier, 5 is a carrier recovery circuit, 6 is a complex multiplier for demodulation, 7 is a clock recovery circuit.
An inputted IF band signal which is phase-modulated in M phases is detected in the quasi-coherent detection circuit 2 and a quasi-coherent demodulated signal is outputted. The quasi-coherent demodulated signal is converted in the A/D converter 3 based on a clock signal supplied from the clock recovery circuit 7 and supplied to the M-th power complex multiplier 4 and the complex multiplier 6. The M-th power complex multiplier 4 multiplies the output of the A/D converter 4 by M and outputs it to the carrier recovery circuit 5. In the carrier recovery circuit 5, the carrier is extracted from the output which is multiplied by M in the A/D converter 3 by using a PLL or the like. The multiplier 6 coherently detects the output of the A/D converter 3 by using the carrier and outputs the demodulated data. The demodulated data is supplied to the clock recovery circuit 7 for clock recovery. The regenerated clock signal is supplied to the A/D converter 3.
Referring to FIG. 13(a), the operation of the conventional clock recovery circuit 7 is as follows. In this figure, points illustrated with the symbols .circle. denote output data obtained when the A/D converter performs sampling at correct timing and when the demodulator 6 also produces correct phase coherent detection. Points marked with the symbol .largecircle. shows zero cross points in the above condition. On the other hand, points illustrated with symbols .quadrature., .DELTA. denote those when sampling timing is shifted out of the correct position. Timing error information can be gotten from the polarities of a point B illustrated with the symbol .DELTA. and points illustrated with symbols .circle. before and behind that point B. A method based on using a phase locked loop (PLL or the like), and based on the timing error information, establishes synchronization of sampling timing. Carrier recovery is in turn achieved in the carrier recovery circuit 5 and coherent detecting demodulation is performed.
Incidentally, the leading portion of a received signal is lost as shown in FIG. 13(b), because the recovery of sampling timing and clocking timing consume a certain time. Also the carrier recovery and the sampling timing recovery are in very close relation, so if one does not go well, the other also does not go well, and in this case an initial operation may not be properly executed.
In FIG. 13, this can be easily understood by the fact that the clock is regenerated from the data which is coherent detected based on the carrier which is regenerated in the carrier recovery circuit 5 and the input signal of the coherent detector (4, 5, 6) is generated in the A/D converter 3 by using the clock.
Thus, the conventional method can not be used in a system wherein received signals are broken frequently by being blocked as in mobile satellite communication system.